ICED: IC Layout Editor
- Makes full use of 386/486/586's 32 bit architecture
- CIF and Stream (Calma-GDSII Outform3) input and output
- Flexible memory management handles databases up to 60 Gigabytes
- Extremely quick installation and configuration
- Simple ASCII technology/command file - (typically 1 page)
- Extremely fast screen refresh, plotting, and export
- Up to 255 drawing layers
- Cells nested up to 16 levels deep
- Edit-in-Place and Subcell edit
- Intelligent zooming limits detail at large scales automatically
- Wires and polygons with sides at "any angle"
- Text and lines for annotation
- Autopan and nested view commands
- User definable patterns, colors, shortcut keys, and menus
- Flexible full-color plotting
- Powerful programming language for user customizable command files
- Interactive DRC is available which enables:
- Boolean processing
- Bloats and shrinks
- Interactive design rule checking
- Platforms: Windows 98, NT4.0, 2000, and XP. Linux version under development.
The DRC: Design Rule Checker
- Very fast design rule checking and error flag creation right on your PC
- Flat DRC with limited hierarchical processing
- Hierarchical layer generation
- Full set of Boolean and bloat/shrink operations
- Full set of shape filtering operations: boxes, circles, aspect ratio, etc.
- Recognition of electrical connections, including well stamping
- Air bridge recognition
- Snaps geometries to grid
- Minimum width, minimum notch width, minimum side
- Minimum and maximum spacing between shapes
- Finds acute angles and self-intersecting shapes
- Enclosure and overlap checks
- Minimum percentages of fill area verified
- Error flags on user specified layers
- Can be used interactively in ICED Layout Editor
The NLE/LVS: Netlist Extractor/Layout vs Schematic
- Device recognition and netlist comparison at fast speeds on PC platforms
- NLE program performs device and net recognition from ICED layout
- Powerful NLE rule deck language
- Enhanced electrical verification of poor conductors (e.g. wells)
- Parasitic device recognition is supported
- LVS program compares netlists: LVL, SVS, and LVS
- Accepts schematic netlists in CDL, SPICE, PSPICE, and HSPICE dialects
- Flexible parameter value checking
- Optional logical merges and collapses before comparison
- Comparison algorithms do not depend on labels, but labels are supported
- Spice language output includes parasitic devices
- Included LPE program converts NLE layout netlist to Spice dialects
- Interactive net tracing in ICED Layout Editor after circuit extraction
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